[all-commits] [llvm/llvm-project] 2db700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

[Austin Kerbow via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2db700215a2eebce7358c0a81a3d52d0a9d4a997
      https://github.com/llvm/llvm-project/commit/2db700215a2eebce7358c0a81a3d52d0a9d4a997
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2022-05-11 (Wed, 11 May 2022)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsAMDGPU.def
    M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
    M clang/test/SemaOpenCL/builtins-amdgcn-error.cl
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp
    M llvm/test/CodeGen/AMDGPU/hazard-pseudo-machineinstrs.mir
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
    A llvm/test/CodeGen/AMDGPU/sched_barrier.mir

  Log Message:
  -----------
  [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

Adds an intrinsic/builtin that can be used to fine tune scheduler behavior. If
there is a need to have highly optimized codegen and kernel developers have
knowledge of inter-wave runtime behavior which is unknown to the compiler this
builtin can be used to tune scheduling.

This intrinsic creates a barrier between scheduling regions. The immediate
parameter is a mask to determine the types of instructions that should be
prevented from crossing the sched_barrier. In this initial patch, there are only
two variations. A mask of 0 means that no instructions may be scheduled across
the sched_barrier. A mask of 1 means that non-memory, non-side-effect inducing
instructions may cross the sched_barrier.

Note that this intrinsic is only meant to work with the scheduling passes. Any
other transformations that may move code will not be impacted in the ways
described above.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D124700