[all-commits] [llvm/llvm-project] 5c7ec9: [RISCV] Fold addiw from (add X, (addiw (lui C1, C2...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c7ec998a916baf8b35d571d0cc11753d464792d
      https://github.com/llvm/llvm-project/commit/5c7ec998a916baf8b35d571d0cc11753d464792d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-11 (Wed, 11 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/mem.ll
    M llvm/test/CodeGen/RISCV/mem64.ll

  Log Message:
  -----------
  [RISCV] Fold addiw from (add X, (addiw (lui C1, C2))) into load/store address

This is a followup to D124231.

We can fold the ADDIW in this pattern if we can prove that LUI+ADDI
would have produced the same result as LUI+ADDIW.

This pattern occurs because constant materialization prefers LUI+ADDIW
for all simm32 immediates. Only immediates in the range
0x7ffff800-0x7fffffff require an ADDIW. Other simm32 immediates
work with LUI+ADDI.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D124693