[all-commits] [llvm/llvm-project] 18ed27: [AMDGPU] gfx11 subtarget features & early tests

Joe Nash via All-commits all-commits at lists.llvm.org
Wed May 11 07:59:21 PDT 2022 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18ed279a3a4aa830830e5cfee3e3824f91c3ca6c
      https://github.com/llvm/llvm-project/commit/18ed279a3a4aa830830e5cfee3e3824f91c3ca6c
  Author: Joe Nash <Joseph.Nash at amd.com>
  Date:   2022-05-11 (Wed, 11 May 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
    M llvm/lib/Target/AMDGPU/GCNProcessors.td
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SISchedule.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
    M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
    M llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
    M llvm/test/CodeGen/AMDGPU/gws-hazards.mir
    M llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir
    M llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
    M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
    M llvm/test/CodeGen/AMDGPU/machine-cse-commute-target-flags.mir
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
    M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
    M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir

  Log Message:
  -----------
  [AMDGPU] gfx11 subtarget features & early tests

Tablegen definitions for subtarget features and cpp predicate functions to
access the features.
New Sub-TargetProcessors and common latencies.
Simple changes to MIR codegen tests which pass on gfx11 because they have the
same output as previous subtargets or operate on pseudo instructions which
are reused from previous subtargets.

Contributors:
Jay Foad <jay.foad at amd.com>
Petar Avramovic <Petar.Avramovic at amd.com>

Patch 4/N for upstreaming of AMDGPU gfx11 architecture

Depends on D124538

Reviewed By: Petar.Avramovic, foad

Differential Revision: https://reviews.llvm.org/D125261

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