[all-commits] [llvm/llvm-project] 7ed16e: [riscv] Fix state tracking bug on vsetvli (phi of ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ed16e7c510a8b8e82fbf7d48a2d6d108f9c3748
      https://github.com/llvm/llvm-project/commit/7ed16e7c510a8b8e82fbf7d48a2d6d108f9c3748
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-09 (Mon, 09 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

  Log Message:
  -----------
  [riscv] Fix state tracking bug on vsetvli (phi of vsetvli) peephole

This fixes the first of several cases where the state computed in phase 1 and 2 of the algorithm differs from the state computed during phase 3. Note that such differences can cause miscompiles by creating disagreements about contents of the VL and VTYPE registers at block boundaries.

In this particular case, we recognize that for the first vsetvli in a block, that if the AVL is a phi of GPR results from previous vsetvlis and the VTYPE field matches, we can avoid emitting a vsetvli as the register contents don't change. Unfortunately, the abstract state does change and that update was lost.

As noted in the test change, this can actually improve results by preserving information until later state transitions in the block. However, this minor codegen improvement is not the motivation for the patch. The motivation is to avoid cases a case where we break a key internal correctness invariant.

Differential Revision: https://reviews.llvm.org/D125133