[all-commits] [llvm/llvm-project] 7dcd0e: [AArch64] Generate AND in place of CSEL for predic...

Rahul via All-commits all-commits at lists.llvm.org
Mon May 9 02:28:32 PDT 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7dcd0ea683ed3175bc3ec6aed24901a9d504182e
      https://github.com/llvm/llvm-project/commit/7dcd0ea683ed3175bc3ec6aed24901a9d504182e
  Author: Rahul Anand R <rahul at rrlogic.co.in>
  Date:   2022-05-09 (Mon, 09 May 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll

  Log Message:
  -----------
  [AArch64] Generate AND in place of CSEL for predicated CTTZ

This patch implements a for a target specific optimization that replaces
the cmp and csel from cttz with an and mask.

Differential Revision: https://reviews.llvm.org/D123782




More information about the All-commits mailing list