[all-commits] [llvm/llvm-project] 2ca78d: [SelectionDAG] Improve asserts in SelectionDAG::ge...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ca78d2bdfaf14e0cfd20dfa5ee53c6d12643e07
      https://github.com/llvm/llvm-project/commit/2ca78d2bdfaf14e0cfd20dfa5ee53c6d12643e07
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-06 (Fri, 06 May 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h

  Log Message:
  -----------
  [SelectionDAG] Improve asserts in SelectionDAG::getSelect.

The VT passed in must match the type of LHS and RHS.
Previously we only checked that the vectorness matched.