[all-commits] [llvm/llvm-project] 76f90a: [SelectionDAG] Clear promoted bits before UREM on ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 76f90a9d71ee0e6d7ad1f9d67a66d97112328f82
      https://github.com/llvm/llvm-project/commit/76f90a9d71ee0e6d7ad1f9d67a66d97112328f82
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-06 (Fri, 06 May 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/funnel-shift.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/ARM/funnel-shift.ll
    M llvm/test/CodeGen/Mips/funnel-shift.ll
    M llvm/test/CodeGen/PowerPC/funnel-shift.ll
    M llvm/test/CodeGen/X86/funnel-shift.ll

  Log Message:
  -----------
  [SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

Otherwise we have garbage in the upper bits that can affect the
results of the UREM.

Fixes PR55296.

Differential Revision: https://reviews.llvm.org/D125076