[all-commits] [llvm/llvm-project] 084f96: [SelectionDAG] Constant fold (sext_inreg undef, VT...

Craig Topper via All-commits all-commits at lists.llvm.org
Thu May 5 09:45:53 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 084f967370fcd9a2964da0ff09c1970ebcc721c6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-05 (Thu, 05 May 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/pr55178.ll
    M llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll

  Log Message:
  [SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef.

The result of sign_extend_inreg needs to have as many sign bits
as requested by the VT argument. The easiest way to guarantee this
is to fold it to 0.

SystemZ test was modified to avoid using undef.

Fixes https://github.com/llvm/llvm-project/issues/55178

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D124696

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