[all-commits] [llvm/llvm-project] ba6c8d: [AMDGPU] Combine DPP mov even if old reg def is in...
Jay Foad via All-commits
all-commits at lists.llvm.org
Thu May 5 03:34:06 PDT 2022
Author: Jay Foad <jay.foad at amd.com>
Date: 2022-05-05 (Thu, 05 May 2022)
[AMDGPU] Combine DPP mov even if old reg def is in different BB
Given a DPP mov like this:
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
this patch just removes a check that %2 (the "old reg") was defined in
the same BB as the DPP mov instruction. GCNDPPCombine requires that the
MIR is in SSA form so I don't understand why the BB matters.
This lets the optimization work in more real world cases when the
definition of %2 gets hoisted out of a loop.
Differential Revision: https://reviews.llvm.org/D124182
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