[all-commits] [llvm/llvm-project] 373ce1: [X86][AMX] Replace PXOR instruction with SET0 in A...

[Luo, Yuanke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 373ce147602cb2007ac861bc1956c16f473780a6
      https://github.com/llvm/llvm-project/commit/373ce147602cb2007ac861bc1956c16f473780a6
  Author: Luo, Yuanke <yuanke.luo at intel.com>
  Date:   2022-05-05 (Thu, 05 May 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86PreTileConfig.cpp
    M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
    M llvm/test/CodeGen/X86/AMX/amx-config.ll
    M llvm/test/CodeGen/X86/AMX/amx-intrinsic-chain.ll
    M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
    M llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
    M llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
    M llvm/test/CodeGen/X86/AMX/amx-spill.ll
    M llvm/test/CodeGen/X86/AMX/amx-tile-basic.ll

  Log Message:
  -----------
  [X86][AMX] Replace PXOR instruction with SET0 in AMX pre config.

To generate zero value, the PXOR instruction need 3 operands that is
tied to the same vreg. If is not good in SSA form and with undef value
two address instruction pass may convert
`%0:vr128 = PXORrr undef %0, undef %0`
to `%1:vr128 = PXORrr undef %1:vr128(tied-def 0), undef %0:vr128`.
It is not expected.
It can be simplified to SET0 instruction which only take 1 destination
operand. It should be more friendly to two address instruction pass and
register allocation pass.
`%0:vr128 = V_SET0`
Also add AVX1 code path so that it is consistant to other code.

Differential Revision: https://reviews.llvm.org/D124903