[all-commits] [llvm/llvm-project] 411bb4: [RISCV] Add a special case to treat riscv-v-vector...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 411bb42eed723ba8e8ae29a59cbc7aacc6bab774
      https://github.com/llvm/llvm-project/commit/411bb42eed723ba8e8ae29a59cbc7aacc6bab774
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-04 (Wed, 04 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

  Log Message:
  -----------
  [RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value.

riscv-v-vector-bits-min is primarily used to opt-in to the
autovectorizer. The vector width can be determined from Zvl*b.

This patch adds support treating -1 as meaning use Zvl*b so we can
still opt-in to autovectorization without needing to repeat a
vector width already given by Zvl*b or -mcpu.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D124960