[all-commits] [llvm/llvm-project] 411bb4: [RISCV] Add a special case to treat riscv-v-vector...
Craig Topper via All-commits
all-commits at lists.llvm.org
Wed May 4 14:37:02 PDT 2022
Author: Craig Topper <craig.topper at sifive.com>
Date: 2022-05-04 (Wed, 04 May 2022)
[RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value.
riscv-v-vector-bits-min is primarily used to opt-in to the
autovectorizer. The vector width can be determined from Zvl*b.
This patch adds support treating -1 as meaning use Zvl*b so we can
still opt-in to autovectorization without needing to repeat a
vector width already given by Zvl*b or -mcpu.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D124960
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