[all-commits] [llvm/llvm-project] 1d6430: [RISCV] Update isLegalAddressingMode for RVV.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1d6430b9e2b82ebb9a90632f3b39c892548528d6
      https://github.com/llvm/llvm-project/commit/1d6430b9e2b82ebb9a90632f3b39c892548528d6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-03 (Tue, 03 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

  Log Message:
  -----------
  [RISCV] Update isLegalAddressingMode for RVV.

RVV instructions only support base register addressing.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D124820