[all-commits] [llvm/llvm-project] 4e5e04: [LoopVectorize] Support reductions that store inte...

[Igor Kirillov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e5e042d9a4a842c6744d91ef1359403dee2edbb
      https://github.com/llvm/llvm-project/commit/4e5e042d9a4a842c6744d91ef1359403dee2edbb
  Author: Igor Kirillov <Igor.Kirillov at arm.com>
  Date:   2022-05-03 (Tue, 03 May 2022)

  Changed paths:
    M llvm/include/llvm/Analysis/IVDescriptors.h
    M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
    M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
    M llvm/lib/Analysis/IVDescriptors.cpp
    M llvm/lib/Analysis/LoopAccessAnalysis.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
    M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing.ll

  Log Message:
  -----------
  [LoopVectorize] Support reductions that store intermediary result

Adds ability to vectorize loops containing a store to a loop-invariant
address as part of a reduction that isn't converted to SSA form due to
lack of aliasing info. Runtime checks are generated to ensure the store
does not alias any other accesses in the loop.

Ordered fadd reductions are not yet supported.

Differential Revision: https://reviews.llvm.org/D110235