[all-commits] [llvm/llvm-project] f91690: [RISCV] Don't merge addi into load/store address i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f91690f7db96aae16425241a17fe6649f5d156b4
      https://github.com/llvm/llvm-project/commit/f91690f7db96aae16425241a17fe6649f5d156b4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-29 (Fri, 29 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/mem.ll

  Log Message:
  -----------
  [RISCV] Don't merge addi into load/store address if addi has a FrameIndex operand.

This fixes a crash from D124231.

We can't fold
  (load (add base, (addi src, off1)), off2)
     -> (load (add base, src), off1+off2)
if the src is a FrameIndex. FrameIndex cannot be the operand of an
add.

There was an immediate==0 check that I think was trying to catch
the common case of FrameIndex addis where the immediate is 0, but
they can also appear in non-zero form. Instead explicitly check
for a FrameIndex operand.