[all-commits] [llvm/llvm-project] 5c3837: [RISCV] Improve constant materialization for cases...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c3837312503b4ef8443951194127c4ba2a03153
      https://github.com/llvm/llvm-project/commit/5c3837312503b4ef8443951194127c4ba2a03153
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-29 (Fri, 29 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll
    M llvm/test/MC/RISCV/rv64i-aliases-valid.s
    M llvm/test/MC/RISCV/rv64zbs-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.

It's possible that we have a constant that isn't simm32 so we can't
use LUI+ADDIW, but we can use LUI+ADDI. Because ADDI uses a sign
extended constant, it's possible that after subtracting it out, we
end up with a simm32 that maps to LUI.

This patch detects this case after removing Lo12 and before shifting
the value for SLLI.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D124222