[all-commits] [llvm/llvm-project] c62b01: [RISCV] Merge addi into load/store as there is a A...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c62b014db97953bee25d17b46730f05eea6a3430
      https://github.com/llvm/llvm-project/commit/c62b014db97953bee25d17b46730f05eea6a3430
  Author: Hsiangkai Wang <hsiangkai at google.com>
  Date:   2022-04-29 (Fri, 29 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/large-stack.ll
    M llvm/test/CodeGen/RISCV/mem.ll
    M llvm/test/CodeGen/RISCV/mem64.ll

  Log Message:
  -----------
  [RISCV] Merge addi into load/store as there is a ADD between them

This patch adds peephole optimizations for the following patterns:

(load (add base, (addi src, off1)), off2)
   -> (load (add base, src), off1+off2)
(store val, (add base, (addi src, off1)), off2)
   -> (store val, (add base, src), off1+off2)

Differential Revision: https://reviews.llvm.org/D124231