[all-commits] [llvm/llvm-project] 28d09b: [CodeGen][ARM] Enable Swing Module Scheduling for ARM

[dpenry via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 28d09bbbc3d09c912b54a4d5edb32cab7de32a6f
      https://github.com/llvm/llvm-project/commit/28d09bbbc3d09c912b54a4d5edb32cab7de32a6f
  Author: David Penry <david.penry at arm.com>
  Date:   2022-04-28 (Thu, 28 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachinePipeliner.h
    M llvm/include/llvm/CodeGen/ModuloSchedule.h
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    M llvm/lib/CodeGen/ModuloSchedule.cpp
    M llvm/lib/Target/ARM/ARM.td
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMSubtarget.cpp
    M llvm/lib/Target/ARM/ARMSubtarget.h
    M llvm/lib/Target/ARM/ARMTargetMachine.cpp
    M llvm/test/CodeGen/ARM/O3-pipeline.ll
    A llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
    A llvm/test/CodeGen/Thumb2/swp-fixedii.mir

  Log Message:
  -----------
  [CodeGen][ARM] Enable Swing Module Scheduling for ARM

This patch permits Swing Modulo Scheduling for ARM targets
turns it on by default for the Cortex-M7.  The t2Bcc
instruction is recognized as a loop-ending branch.

MachinePipeliner is extended by adding support for
"unpipelineable" instructions.  These instructions are
those which contribute to the loop exit test; in the SMS
papers they are removed before creating the dependence graph
and then inserted into the final schedule of the kernel and
prologues. Support for these instructions was not previously
necessary because current targets supporting SMS have only
supported it for hardware loop branches, which have no
loop-exit-contributing instructions in the loop body.

The current structure of the MachinePipeliner makes it difficult
to remove/exclude these instructions from the dependence graph.
Therefore, this patch leaves them in the graph, but adds a
"normalization" method which moves them in the schedule to
stage 0, which causes them to appear properly in kernel and
prologues.

It was also necessary to be more careful about boundary nodes
when iterating across successors in the dependence graph because
the loop exit branch is now a non-artificial successor to
instructions in the graph. In additional, schedules with physical
use/def pairs in the same cycle should be treated as creating an
invalid schedule because the scheduling logic doesn't respect
physical register dependence once scheduled to the same cycle.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D122672