[all-commits] [llvm/llvm-project] ec11fb: [RISCV] Use default promotion for (i32 (shl 1, X))...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ec11fbb1d682e9c3e67eafc036c92fe9200b40f5
      https://github.com/llvm/llvm-project/commit/ec11fbb1d682e9c3e67eafc036c92fe9200b40f5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-28 (Thu, 28 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64zbs.ll

  Log Message:
  -----------
  [RISCV] Use default promotion for (i32 (shl 1, X)) on RV64 when Zbs is enabled.

This improves opportunities to use bset/bclr/binv. Unfortunately,
there are no W versions of these instrcutions so this isn't always
a clear win. If we use SLLW we get free sign extend and shift masking,
but need to put a 1 in a register and can't remove an or/xor. If
we use bset/bclr/binv we remove the immediate materializationg and
logic op, but might need a mask on the shift amount and sext.w.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D124096