[all-commits] [llvm/llvm-project] 4e5dee: [mlir][ods] Add tablegen field for concise printin...

[Jeremy Furtek via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e5dee2f30dd5b3548a268271e844b54a35947c2
      https://github.com/llvm/llvm-project/commit/4e5dee2f30dd5b3548a268271e844b54a35947c2
  Author: jfurtek <jfurtek at nvidia.com>
  Date:   2022-04-25 (Mon, 25 Apr 2022)

  Changed paths:
    M mlir/include/mlir/IR/EnumAttr.td
    M mlir/include/mlir/TableGen/Attribute.h
    M mlir/lib/TableGen/Attribute.cpp
    M mlir/tools/mlir-tblgen/EnumsGen.cpp
    M mlir/unittests/TableGen/EnumsGenTest.cpp
    M mlir/unittests/TableGen/enums.td

  Log Message:
  -----------
  [mlir][ods] Add tablegen field for concise printing of BitEnum attributes

This diff introduces a tablegen field for bit enum attributes
(`printBitEnumPrimaryGroups`) to control printing when the enum uses "group"
cases. An example would be an implementation that uses a `fastmath` enum value
as an alias for individual fastmath flags. The proposed field would allow
printing of simply `fast` for the enum value, instead of the more verbose list
that would include `fast` as well as the individual flags (e.g. `reassoc,nnan,
ninf,nsz,arcp,contract,afn,fast`).

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D123871