[all-commits] [llvm/llvm-project] 40f1af: [RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XO...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 40f1af47601044149102b1597d5f56689661f8a5
      https://github.com/llvm/llvm-project/commit/40f1af47601044149102b1597d5f56689661f8a5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-25 (Mon, 25 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    A llvm/test/CodeGen/RISCV/machine-cse.ll

  Log Message:
  -----------
  [RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D123970