[all-commits] [llvm/llvm-project] ffe03f: [RISCV] Fix incorrect policy implement for unmaske...

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ffe03ff75c26d598ce71d19c5eacf528f63a670b
      https://github.com/llvm/llvm-project/commit/ffe03ff75c26d598ce71d19c5eacf528f63a670b
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2022-04-25 (Mon, 25 Apr 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

  Log Message:
  -----------
  [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

vslideup works by leaving elements 0<i<OFFSET undisturbed.
so it need the destination operand as input for correctness
regardless of policy. Add a operand to indicate policy.

We also add policy operand for unmaksed vslidedown to keep the interface consistent with vslideup
because vslidedown have only undisturbed at 0<i<vstart but user have no way to control of vstart.

Reviewed By: rogfer01, craig.topper

Differential Revision: https://reviews.llvm.org/D124186