[all-commits] [llvm/llvm-project] 5bd4bc: [mlir] Modify SuperVectorize to generate select op...

[Amy Zhuang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5bd4bcfc049670946d010eef7b1d22be4c5b303a
      https://github.com/llvm/llvm-project/commit/5bd4bcfc049670946d010eef7b1d22be4c5b303a
  Author: Amy Zhuang <amy.zhuang at intel.com>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
    M mlir/test/Dialect/Affine/SuperVectorize/vectorize_reduction.mlir

  Log Message:
  -----------
  [mlir] Modify SuperVectorize to generate select op->combiner op

Insert the select op before the combiner op when vectorizing a
reduction loop that needs a mask, so the vectorized reduction loop
can pass isLoopParallel check and be transformed correctly in later
passes.

Reviewed By: dcaballe

Differential Revision: https://reviews.llvm.org/D124047