[all-commits] [llvm/llvm-project] 953481: [RISCV] Teach generateInstSeqImpl to generate BSET...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9534811aa8dddec84520776ec027721f062362eb
      https://github.com/llvm/llvm-project/commit/9534811aa8dddec84520776ec027721f062362eb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/test/CodeGen/RISCV/imm.ll

  Log Message:
  -----------
  [RISCV] Teach generateInstSeqImpl to generate BSETI for single bit cases.

If the immediate has one bit set, but isn't a simm32 we can try
the BSETI instruction from Zbs.