[all-commits] [llvm/llvm-project] 4e0dac: AMDGPU/GlobalISel: Precommit test for D124163

[petar-avramovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e0dacb2cf325158c3c672f45202ab166aec99b0
      https://github.com/llvm/llvm-project/commit/4e0dacb2cf325158c3c672f45202ab166aec99b0
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Precommit test for D124163


  Commit: e06290e53f2880962fef582f118482d70f1c27f0
      https://github.com/llvm/llvm-project/commit/e06290e53f2880962fef582f118482d70f1c27f0
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix isVCC for uniform s1 with reg class on wave32

Fix isVCC for register that was assigned register class during
inst-selection. This happens when register has multiple uses.
For wave32, uniform i1 to vcc copy was selected like vcc to vcc
copy when uniform i1 had assigned register class.
Uniform i1 register with assigned register class will have s1 LLT,
be defined using G_TRUNC and class will be SReg_32RegClass.
Vcc i1 register with assigned register class will have s1 LLT,
class will be SReg_32RegClass for wave32 and SReg_64RegClass for
wave64 and register will not be defined by G_TRUNC.

Differential Revision: https://reviews.llvm.org/D124163


Compare: https://github.com/llvm/llvm-project/compare/ead231dec0fc...e06290e53f28