[all-commits] [llvm/llvm-project] 3e678c: [RISCV] Don't emit fractional VIDs with negative s...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e678cb77264907fbc2899c291ce23af308073ff
      https://github.com/llvm/llvm-project/commit/3e678cb77264907fbc2899c291ce23af308073ff
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

  Log Message:
  -----------
  [RISCV] Don't emit fractional VIDs with negative steps

We can't shift-right negative numbers to divide them, so avoid emitting
such sequences. Use negative numerators as a proxy for this situation, since
the indices are always non-negative.

An alternative strategy could be to add a compiler flag to emit division
instructions, which would at least allow us to test the VID sequence
matching itself.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D123796