[all-commits] [llvm/llvm-project] 2f4916: [DAG]Introduce llvm::processShuffleMasks and use i...

[Andrew V. Tischenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f49163b3365e5dc046b03e422a048dd45aee3f0
      https://github.com/llvm/llvm-project/commit/2f49163b3365e5dc046b03e422a048dd45aee3f0
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2022-04-20 (Wed, 20 Apr 2022)

  Changed paths:
    M llvm/include/llvm/Analysis/VectorUtils.h
    M llvm/lib/Analysis/VectorUtils.cpp
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/AArch64/insert-extend.ll
    M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
    M llvm/test/CodeGen/AArch64/shuffles.ll
    M llvm/test/CodeGen/ARM/fp16-insert-extract.ll
    M llvm/test/CodeGen/PowerPC/pr27078.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4.ll
    M llvm/test/CodeGen/X86/haddsub-4.ll
    M llvm/test/CodeGen/X86/insertelement-duplicates.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/pr34592.ll
    M llvm/test/CodeGen/X86/pr44976.ll
    M llvm/test/CodeGen/X86/splat-for-size.ll
    M llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
    M llvm/test/CodeGen/X86/x86-interleaved-access.ll

  Log Message:
  -----------
  [DAG]Introduce llvm::processShuffleMasks and use it for shuffles in DAG Type Legalizer.

We can process the long shuffles (working across several actual
vector registers) in the best way if we take the actual register
represantion into account. We can build more correct representation of
register shuffles, improve number of recognised buildvector sequences.
Also, same function can be used to improve the cost model for the
shuffles. in future patches.

Part of D100486

Differential Revision: https://reviews.llvm.org/D115653