[all-commits] [llvm/llvm-project] cc9495: [AArch64] Only mark cost 1 perfect shuffles as legal

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc9495f6791aaaacbff55d7eace43550eb27e3c9
      https://github.com/llvm/llvm-project/commit/cc9495f6791aaaacbff55d7eace43550eb27e3c9
  Author: David Green <david.green at arm.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-wide-shuffle.ll
    M llvm/test/CodeGen/AArch64/build-vector-extract.ll
    M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
    M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
    M llvm/test/CodeGen/AArch64/shuffles.ll

  Log Message:
  -----------
  [AArch64] Only mark cost 1 perfect shuffles as legal

The perfect shuffle tables encode a cost of either 0 (a nop-copy) or 1
(a single instruction) with a cost encoding of 0 in the upper 2 bits.
All perfect shuffles with any cost are then marked as legal shuffles
though (the maximum encoded cost is 3), which can confuse the DAG
combiner into thinking the shuffles are cheaper than the should be.

Limiting legal shuffles to single instructions seems to do better in
most case, producing less instructions for complex shuffles. There are
some cases that now become tbl, which may be better or worse depending
on whether the instruction is in a loop and the tbl load can be hoisted
out.

Differential Revision: https://reviews.llvm.org/D123377