[all-commits] [llvm/llvm-project] 33504b: [PowerPC] Allow absolute expressions in relocations

Jeremy Morse via All-commits all-commits at lists.llvm.org
Mon Apr 18 17:10:05 PDT 2022

  Branch: refs/heads/release/14.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 33504b3bbe10d5d4caae13efcb99bd159c126070
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2022-04-18 (Mon, 18 Apr 2022)

  Changed paths:
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    A llvm/test/MC/PowerPC/ppc64-abs-reloc.s

  Log Message:
  [PowerPC] Allow absolute expressions in relocations

The Linux kernel build uses absolute expressions suffixed with @lo/@ha
relocations. This currently doesn't work for DS/DQ form instructions and
there is no reason for it not to. It also works with GAS.
This patch allows this as long as the value is a multiple of 4/16
for DS/DQ form.

Differential revision: https://reviews.llvm.org/D115419

(cherry picked from commit 2aaba44b5c2265f90ac9f0ae188417ef79201c82)

  Commit: 09fba23d41f775e1cee48f56061710d5861c48d2
  Author: Carlo Marcelo Arenas Belón <carenas at gmail.com>
  Date:   2022-04-18 (Mon, 18 Apr 2022)

  Changed paths:
    M compiler-rt/lib/builtins/clear_cache.c

  Log Message:
  [compiler-rt] Implement __clear_cache on FreeBSD/powerpc

dd9173420f06 (Add clear_cache implementation for ppc64. Fix buffer to
meet ppc64 alignment., 2017-07-28), adds an implementation for
__builtin___clear_cache on powerpc64, which was promptly ammended to
also be used with big endian mode in f67036b62c0c (This ppc64 implementation
of clear_cache works for both big and little endian., 2017-08-02)

clang will use this implementation for it's builtin on FreeBSD and result
in an abort() in the cases where 32-bit generation was requested (ex in
macppc or when the big endian powerpc64 build was done with "-m32") and as
reported[1] recently with pcre2, but there is no reason why the same code
couldn't be used in those cases, so use instead the more generic identifier
for the PowerPC architecture.

While at it, update the comment to reflect that POWER8/9 have a 128 byte
wide cache line and so the code could instead use 64 byte windows instead
but that possible optimization has been punted for now.

[1] https://github.com/PhilipHazel/pcre2/issues/92

Reviewed By: jhibbits, #powerpc, MaskRay

Differential Revision: https://reviews.llvm.org/D122640

(cherry picked from commit 81f5c6270cdfcdf80e6296df216b696a7a37c8b5)

  Commit: e8f03f2057ee783439229391a14b2ffe17346100
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2022-04-18 (Mon, 18 Apr 2022)

  Changed paths:
    M lld/COFF/DebugTypes.cpp

  Log Message:
  Force GHashCell to be 8-byte-aligned.

Otherwise, with recent versions of libstdc++, clang can't tell that the
atomic operations are properly aligned, and generates calls to
libatomic.  (Actually, because of the use of reinterpret_cast, it wasn't
guaranteed to be aligned, but I think it ended up being aligned in

Fixes https://github.com/llvm/llvm-project/issues/54790 , the part where
LLVM failed to build.

Differential Revision: https://reviews.llvm.org/D123872

(cherry picked from commit 13fc1781735a327699d9522e8e44899acf92a61a)

  Commit: 0f56ce0fb2079c8f1fdcb7f7199d7313f81a863d
  Author: Jeremy Morse <jeremy.morse at sony.com>
  Date:   2022-04-18 (Mon, 18 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/FastISel.h
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/include/llvm/CodeGen/SelectionDAGISel.h
    M llvm/lib/CodeGen/MachineFunction.cpp
    M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
    M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
    M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    A llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll

  Log Message:
  [DebugInfo][InstrRef] Avoid a crash from mixed variable location modes

Variable locations now come in two modes, instruction referencing and
DBG_VALUE. At -O0 we pick DBG_VALUE to allow fast construction of variable
information. Unfortunately, SelectionDAG edits the optimisation level in
the presence of opt-bisect-limit, meaning different passes have different
views of what variable location mode we should use. That causes assertions
when they're mixed.

This patch plumbs through a boolean in SelectionDAG from start to
instruction emission, so that we don't rely on the current optimisation
level for correctness.

Differential Revision: https://reviews.llvm.org/D123033

(cherry picked from commit fb6596f1ecab652b5b90cf2e395d64112504c1f8)

Compare: https://github.com/llvm/llvm-project/compare/3400d0293a14...0f56ce0fb207

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