[all-commits] [llvm/llvm-project] df29ec: AMDGPU: Select i8/i16 global and flat atomic load/...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: df29ec2f548ba717f80270952ca5754131c4e1fb
      https://github.com/llvm/llvm-project/commit/df29ec2f548ba717f80270952ca5754131c4e1fb
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/BUFInstructions.td
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics.ll

  Log Message:
  -----------
  AMDGPU: Select i8/i16 global and flat atomic load/store

As far as I know these should be atomic anyway, as long as the address
is aligned. Unaligned atomics hit an ugly error in AtomicExpand.


  Commit: 3217ca0863681c5e73e1e0f19e9de350249c45b8
      https://github.com/llvm/llvm-project/commit/3217ca0863681c5e73e1e0f19e9de350249c45b8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    A llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
    M llvm/tools/llvm-reduce/ReducerWorkItem.cpp

  Log Message:
  -----------
  llvm-reduce: Copy register allocation hints to clone


  Commit: e33b07f8599523e1e39b20b134dfc870635353bc
      https://github.com/llvm/llvm-project/commit/e33b07f8599523e1e39b20b134dfc870635353bc
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/tools/llvm-reduce/ReducerWorkItem.cpp

  Log Message:
  -----------
  llvm-reduce: Inform MRI of used phys reg masks

I'm not sure how to directly observe this invisible cache for a test.


Compare: https://github.com/llvm/llvm-project/compare/7c71ce97e7be...e33b07f85995