[all-commits] [llvm/llvm-project] 4975c3: MachineFunction: Remove unused field

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4975c3a9494c37997774bf9254ff79a85c5e5c7f
      https://github.com/llvm/llvm-project/commit/4975c3a9494c37997774bf9254ff79a85c5e5c7f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineFunction.h

  Log Message:
  -----------
  MachineFunction: Remove unused field


  Commit: 6f3f19a36b72e6cc91318f61386ba4fbda8bb388
      https://github.com/llvm/llvm-project/commit/6f3f19a36b72e6cc91318f61386ba4fbda8bb388
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
    M llvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp

  Log Message:
  -----------
  llvm-reduce: Fix some copy-pasted comment errors


  Commit: 9196f5dab757cc2d2f59b5295140fb1f7f4354c2
      https://github.com/llvm/llvm-project/commit/9196f5dab757cc2d2f59b5295140fb1f7f4354c2
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/MachineCSE.cpp
    A llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir

  Log Message:
  -----------
  MachineCSE: Report this requires SSA


  Commit: a0f9e4ed2a472f0a41a4d292a9c5fc939ae064ad
      https://github.com/llvm/llvm-project/commit/a0f9e4ed2a472f0a41a4d292a9c5fc939ae064ad
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    A llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
    M llvm/tools/llvm-reduce/ReducerWorkItem.cpp
    M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp

  Log Message:
  -----------
  llvm-reduce: Fix handling of generic virtual registers

Try to preserve register banks, types and names. Fixes the lowest
hanging fruit in issue 54894.


  Commit: b4ace5da45672bbfa36c9adc74f5399d1ccd8a65
      https://github.com/llvm/llvm-project/commit/b4ace5da45672bbfa36c9adc74f5399d1ccd8a65
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    A llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
    M llvm/tools/llvm-reduce/ReducerWorkItem.cpp

  Log Message:
  -----------
  llvm-reduce: Fix asserting on undef virtual registers

This was only populating the virtual register map for def operands
that appeared in the function, but that may not exist if there are
only undef uses.


  Commit: c528fbf8824b5004f9ff895de392ef731644edea
      https://github.com/llvm/llvm-project/commit/c528fbf8824b5004f9ff895de392ef731644edea
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/dpp_combine.mir

  Log Message:
  -----------
  AMDGPU: Fix assert if v_mov_b32_dpp is last instruction in the block

This can happen if the use instruction is a phi.

Fixes issue 49961


Compare: https://github.com/llvm/llvm-project/compare/1255e9734880...c528fbf8824b