[all-commits] [llvm/llvm-project] 5c9eed: [libc++] Make __dir_stream visibility declaration ...

[Florian Hahn via All-commits]

  Branch: refs/heads/release/14.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c9eed741dbd32bf3de6ba177a56224822e976bb
      https://github.com/llvm/llvm-project/commit/5c9eed741dbd32bf3de6ba177a56224822e976bb
  Author: Dimitry Andric <dimitry at andric.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M libcxx/include/__filesystem/directory_entry.h

  Log Message:
  -----------
  [libc++] Make __dir_stream visibility declaration consistent

The class `__dir_stream` is currently declared in two places: as a
top-level forward declaration in `directory_iterator.h`, and as a friend
declaration in class `directory_entry`, in `directory_entry.h`.

The former has a `_LIBCPP_HIDDEN` attribute, but the latter does not,
causing the Firefox build to complain about the visibility not matching
the previous declaration. This is because Firefox plays games with
pushing and popping visibility.

Work around this by making both `__dir_stream` declarations consistently
use `_LIBCPP_HIDDEN`.

Reviewed By: ldionne, philnik, #libc

Differential Revision: https://reviews.llvm.org/D121639

(cherry picked from commit 7ab1ab0db40158e6f0794637054c98376e236a6d)


  Commit: 87599bdabbd16f109d317af1164de5a02ff0aca4
      https://github.com/llvm/llvm-project/commit/87599bdabbd16f109d317af1164de5a02ff0aca4
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    A llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
    M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.h
    A llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir

  Log Message:
  -----------
  [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file

RISCVMachineFunctionInfo has some fields like VarArgsFrameIndex and
VarArgsSaveSize are calculated at ISel lowering stage, those info are
not contained in MIR files, that cause test cases rely on those field
can't not reproduce correctly by MIR dump files.

This patch adding the MIR read/write for those fields.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D123178


  Commit: b6e91d4a331e6e3af178f16347ad308237f90340
      https://github.com/llvm/llvm-project/commit/b6e91d4a331e6e3af178f16347ad308237f90340
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir

  Log Message:
  -----------
  [RISCV] Pre-commit for fixing stack offset for RVV object

Reviewed By: rogfer01, frasercrmck

Differential Revision: https://reviews.llvm.org/D123179


  Commit: d0f27fb449525528a5688b7678dd9a8082bb6c41
      https://github.com/llvm/llvm-project/commit/d0f27fb449525528a5688b7678dd9a8082bb6c41
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir

  Log Message:
  -----------
  [RISCV] Fixing stack offset for RVV object with vararg in stack.

We found LLVM generate wrong stack offset for RVV object when stack
having variable argument, that cause by we didn't count vaarg part during
calculate RVV stack objects.

Also update the stack layout diagram for including vaarg in the diagram.

Stack layout ref:
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.cc#L3941

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D123180


  Commit: 2c4d288eae8b21f0f62d4831113b131fdb15f1da
      https://github.com/llvm/llvm-project/commit/2c4d288eae8b21f0f62d4831113b131fdb15f1da
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    A llvm/test/CodeGen/MIR/RISCV/lit.local.cfg

  Log Message:
  -----------
  [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/


  Commit: fe8a27acd716a42667f5a572f52f2b04636010ff
      https://github.com/llvm/llvm-project/commit/fe8a27acd716a42667f5a572f52f2b04636010ff
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    A llvm/test/Transforms/LoopVectorize/X86/pr54413-select-interleave-count-loop-with-cost-zero.ll

  Log Message:
  -----------
  [LV] Handle zero cost loops in selectInterleaveCount.

In some case, like in the added test case, we can reach
selectInterleaveCount with loops that actually have a cost of 0.

Unfortunately a loop cost of 0 is also used to communicate that the cost
has not been computed yet. To resolve the crash, bail out if the cost
remains zero after computing it.

This seems like the best option, as there are multiple code paths that
return a cost of 0 to force a computation in selectInterleaveCount.
Computing the cost at multiple places up front there would unnecessarily
complicate the logic.

Fixes #54413.

(cherry picked from commit ecb4171dcbf1b433c9963fd605a74898303e850d)


Compare: https://github.com/llvm/llvm-project/compare/c62053979489...fe8a27acd716