[all-commits] [llvm/llvm-project] 12c102: [AArch64] Lowering and legalization of strict FP16

[john-brawn-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 12c1022679d40e2442c9f6020281c5a010e27dee
      https://github.com/llvm/llvm-project/commit/12c1022679d40e2442c9f6020281c5a010e27dee
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
    M llvm/test/CodeGen/AArch64/fp-intrinsics.ll

  Log Message:
  -----------
  [AArch64] Lowering and legalization of strict FP16

For strict FP16 to work correctly needs some changes in lowering and
legalization:
 * SelectionDAGLegalize::PromoteNode was missing handling for some
   strict fp opcodes.
 * Some of the custom lowering of strict fp operations needed to be
   adjusted to work with FP16.
 * Custom lowering needed to be added for round-to-int operations.

With this, and the previous patches for the rest of the strict fp
isel, we can set IsStrictFPEnabled = true.

Differential Revision: https://reviews.llvm.org/D115620


  Commit: 1b1466c346694c02ff0e30c96a50701b58bc4830
      https://github.com/llvm/llvm-project/commit/1b1466c346694c02ff0e30c96a50701b58bc4830
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M clang/test/CodeGen/aarch64-neon-intrinsics-constrained.c
    M clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics-constrained.c

  Log Message:
  -----------
  [AArch64] Adjust aarch64 constrained intrinsics tests and un-XFAIL

Remove the checking of the generated asm, as that's already tested
elsewhere, and adjust some tests that were expecting the wrong
intrinsic to be generated.

Differential Revision: https://reviews.llvm.org/D118259


  Commit: 27a8735a444fb311838f06f8d0d5b10ca9b541f6
      https://github.com/llvm/llvm-project/commit/27a8735a444fb311838f06f8d0d5b10ca9b541f6
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-04-14 (Thu, 14 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
    A llvm/test/CodeGen/AArch64/strict-fp-opt.ll

  Log Message:
  -----------
  [AArch64] Add mayRaiseFPException to appropriate instructions

This is mostly handled by adding "let mayRaiseFPException = 1" before
the definition of the relevant instruction classes, but there are a
couple of complications:
 * When we have a multiclass where currently some instantiations are
   of instructions that can raise an exception and others aren't we
   need to split that into two multiclasses, one inheriting from the
   other using a multiclass parameter to enable exceptions.
 * In a couple of places in the globalisel instruction selector we
   need to manually set the NoFPExcept flag. There's also another
   place that looks like it should need it, but that code is never hit
   for those opcodes due to them being handled by the generic
   instruction selector, so I've instead just removed them from the
   switch.

Differential Revision: https://reviews.llvm.org/D115352


Compare: https://github.com/llvm/llvm-project/compare/d43d9e1d5c98...27a8735a444f