[all-commits] [llvm/llvm-project] 0e1f4d: [SLP]Improve reductions analysis and emission, par...

[Andrew V. Tischenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0e1f4d4d3cb08ff84df5adc4f5e41d0a2cebc53d
      https://github.com/llvm/llvm-project/commit/0e1f4d4d3cb08ff84df5adc4f5e41d0a2cebc53d
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
    M llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
    M llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
    M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
    M llvm/test/Transforms/SLPVectorizer/slp-umax-rdx-matcher-crash.ll

  Log Message:
  -----------
  [SLP]Improve reductions analysis and emission, part 1.

Currently SLP vectorizer walks through the instructions and selects
3 main classes of values: 1) reduction operations - instructions with same
reduction opcode (add, mul, min/max, etc.), which build the reduction,
2) reduced values - instructions with the same opcodes, but different
from the reduction opcode, 3) extra arguments - all other values,
instructions from the different basic block rather than the root node,
instructions with to many/less uses.

This scheme is not very efficient. It excludes some instructions and all
non-instruction values from the reductions (constants, proficient
gathers), to many possibly reduced values are marked as extra arguments.
Patch improves this process by introducing a bit extended analysis
stage. During this stage, we still try to select 3 classes of the
values: 1) reduction operations - same as before, 2) possibly reduced
values - all instructions from the current block/non-instructions, which
may build a vectorization tree, 3) extra arguments - instructions from
the different basic blocks. Additionally, an extra sorting of the
possibly reduced values occurs to build the scalar sequences which
highly likely will bed vectorized, e.g. loads are grouped by the
distance between them, constants are grouped together, cmp instructions
are sorted by their compare types and predicates, extractelement
instructions are sorted by the vector operand, etc. Also, these groups
are reordered by their length so the longest group is the first in the
list of the possibly reduced values.

The vectorization process tries to emit the reductions for all these
groups. These reductions, remaining non-vectorized possible reduced
values and extra arguments are then combined into the final expression
just like it was before.

Differential Revision: https://reviews.llvm.org/D114171