[all-commits] [llvm/llvm-project] 120c51: Mips/GlobalISel: Add test for atomic load

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 120c5115b86e0ab70fd2e60857a13058e1f3e99a
      https://github.com/llvm/llvm-project/commit/120c5115b86e0ab70fd2e60857a13058e1f3e99a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    A llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_atomic.ll

  Log Message:
  -----------
  Mips/GlobalISel: Add test for atomic load


  Commit: abe171df06a42b163af09e8c08e8bb142a2d90ec
      https://github.com/llvm/llvm-project/commit/abe171df06a42b163af09e8c08e8bb142a2d90ec
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp

  Log Message:
  -----------
  GlobalISel: Update mutationIsSane assert for scalable vectors


  Commit: 95c2bcbf8b98c176408e5cce82afef232b788b18
      https://github.com/llvm/llvm-project/commit/95c2bcbf8b98c176408e5cce82afef232b788b18
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

  Log Message:
  -----------
  GlobalISel: Handle widening umulo/smulo condition outputs


  Commit: 0e489926be00326b09fb4dd51d76c758056d358c
      https://github.com/llvm/llvm-project/commit/0e489926be00326b09fb4dd51d76c758056d358c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  Log Message:
  -----------
  GlobalISel: Handle widening addo/subo booleans

This will be tested in a future patch


  Commit: 3f2cc7cc2b17ea6b7c09470ffc75b4691ce3ea95
      https://github.com/llvm/llvm-project/commit/3f2cc7cc2b17ea6b7c09470ffc75b4691ce3ea95
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir

  Log Message:
  -----------
  GlobalISel: Fix lowerSelect handling of boolean high bits

This was making several invalid assumptions about the incoming
select. First, it was assuming the incoming condition was either s1 or
already sign extended, not accounting for different boolean high bits
behavior between scalar and vector conditions. We only had a vector
boolean due to the intermediate step vector select, which is now
avoided.

Second, it was assuming it can use the result vector type as a boolean
mask. These types don't have anything to do with other, and only makes
sense in the context of the expansion to bit operations. Since these
logically are part of the same lowering, do the complete expansion in
a single step.

The added select_v4s1_s1 test does fail to legalize, since it seems
AArch64's vector legalization support is pretty incomplete.


  Commit: 600912225024663a2d208cb1a3b69aa77795a7ab
      https://github.com/llvm/llvm-project/commit/600912225024663a2d208cb1a3b69aa77795a7ab
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

  Log Message:
  -----------
  AArch64/GlobalISel: Remove pointless s1 legalize rules

These have no net effect on the legalize rules.


  Commit: 3754f60112e393b4744c4e8ce79eb684dedadc56
      https://github.com/llvm/llvm-project/commit/3754f60112e393b4744c4e8ce79eb684dedadc56
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

  Log Message:
  -----------
  GlobalISel: Implement MoreElements for select of vector conditions


Compare: https://github.com/llvm/llvm-project/compare/057c063c9b06...3754f60112e3