[all-commits] [llvm/llvm-project] c33770: [AMDGPU][DOC][NFC] Updated GFX10 assembler syntax ...

dpreobra via All-commits all-commits at lists.llvm.org
Tue Apr 12 05:19:20 PDT 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c33770d87fd15cf6433a49f34aa31663726ea196
      https://github.com/llvm/llvm-project/commit/c33770d87fd15cf6433a49f34aa31663726ea196
  Author: Dmitry Preobrazhensky <d-pre at mail.ru>
  Date:   2022-04-12 (Tue, 12 Apr 2022)

  Changed paths:
    M llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
    M llvm/docs/AMDGPU/gfx10_hwreg.rst
    R llvm/docs/AMDGPU/gfx10_imm16.rst
    R llvm/docs/AMDGPU/gfx10_imm16_1.rst
    R llvm/docs/AMDGPU/gfx10_imm16_2.rst
    A llvm/docs/AMDGPU/gfx10_imm16_73139a.rst
    A llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst
    R llvm/docs/AMDGPU/gfx10_m.rst
    R llvm/docs/AMDGPU/gfx10_m_1.rst
    A llvm/docs/AMDGPU/gfx10_m_254bcb.rst
    A llvm/docs/AMDGPU/gfx10_m_f5d306.rst
    M llvm/docs/AMDGPU/gfx10_msg.rst
    R llvm/docs/AMDGPU/gfx10_saddr.rst
    R llvm/docs/AMDGPU/gfx10_saddr_1.rst
    A llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst
    A llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst
    R llvm/docs/AMDGPU/gfx10_sbase.rst
    A llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst
    A llvm/docs/AMDGPU/gfx10_sbase_020892.rst
    R llvm/docs/AMDGPU/gfx10_sbase_1.rst
    R llvm/docs/AMDGPU/gfx10_sbase_2.rst
    A llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst
    R llvm/docs/AMDGPU/gfx10_sdata.rst
    R llvm/docs/AMDGPU/gfx10_sdata_1.rst
    R llvm/docs/AMDGPU/gfx10_sdata_2.rst
    R llvm/docs/AMDGPU/gfx10_sdata_3.rst
    A llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst
    R llvm/docs/AMDGPU/gfx10_sdata_4.rst
    R llvm/docs/AMDGPU/gfx10_sdata_5.rst
    A llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst
    A llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst
    A llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst
    A llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst
    A llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst
    R llvm/docs/AMDGPU/gfx10_sdst.rst
    A llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst
    R llvm/docs/AMDGPU/gfx10_sdst_1.rst
    R llvm/docs/AMDGPU/gfx10_sdst_2.rst
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    A llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst
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    A llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst
    A llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst
    R llvm/docs/AMDGPU/gfx10_simm32.rst
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    R llvm/docs/AMDGPU/gfx10_simm32_2.rst
    A llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst
    A llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst
    A llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst
    R llvm/docs/AMDGPU/gfx10_soffset.rst
    R llvm/docs/AMDGPU/gfx10_soffset_1.rst
    R llvm/docs/AMDGPU/gfx10_soffset_2.rst
    A llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
    A llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst
    A llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
    R llvm/docs/AMDGPU/gfx10_src.rst
    R llvm/docs/AMDGPU/gfx10_src_1.rst
    R llvm/docs/AMDGPU/gfx10_src_2.rst
    R llvm/docs/AMDGPU/gfx10_src_3.rst
    A llvm/docs/AMDGPU/gfx10_src_37d670.rst
    R llvm/docs/AMDGPU/gfx10_src_4.rst
    R llvm/docs/AMDGPU/gfx10_src_5.rst
    A llvm/docs/AMDGPU/gfx10_src_516946.rst
    R llvm/docs/AMDGPU/gfx10_src_6.rst
    R llvm/docs/AMDGPU/gfx10_src_7.rst
    R llvm/docs/AMDGPU/gfx10_src_8.rst
    A llvm/docs/AMDGPU/gfx10_src_823582.rst
    A llvm/docs/AMDGPU/gfx10_src_c27036.rst
    A llvm/docs/AMDGPU/gfx10_src_cf1cda.rst
    A llvm/docs/AMDGPU/gfx10_src_d5cd94.rst
    A llvm/docs/AMDGPU/gfx10_src_e0345d.rst
    A llvm/docs/AMDGPU/gfx10_src_e9e6db.rst
    R llvm/docs/AMDGPU/gfx10_srsrc.rst
    R llvm/docs/AMDGPU/gfx10_srsrc_1.rst
    A llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst
    A llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst
    R llvm/docs/AMDGPU/gfx10_ssrc.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst
    R llvm/docs/AMDGPU/gfx10_ssrc_1.rst
    R llvm/docs/AMDGPU/gfx10_ssrc_2.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst
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    A llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst
    R llvm/docs/AMDGPU/gfx10_ssrc_4.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst
    R llvm/docs/AMDGPU/gfx10_ssrc_5.rst
    R llvm/docs/AMDGPU/gfx10_ssrc_6.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst
    R llvm/docs/AMDGPU/gfx10_ssrc_7.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst
    R llvm/docs/AMDGPU/gfx10_ssrc_8.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst
    A llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst
    M llvm/docs/AMDGPU/gfx10_tgt.rst
    R llvm/docs/AMDGPU/gfx10_vaddr.rst
    R llvm/docs/AMDGPU/gfx10_vaddr_1.rst
    R llvm/docs/AMDGPU/gfx10_vaddr_2.rst
    R llvm/docs/AMDGPU/gfx10_vaddr_3.rst
    R llvm/docs/AMDGPU/gfx10_vaddr_4.rst
    R llvm/docs/AMDGPU/gfx10_vaddr_5.rst
    A llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst
    A llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst
    A llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst
    A llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst
    A llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst
    A llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst
    R llvm/docs/AMDGPU/gfx10_vdata.rst
    R llvm/docs/AMDGPU/gfx10_vdata0.rst
    R llvm/docs/AMDGPU/gfx10_vdata0_1.rst
    A llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst
    A llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst
    R llvm/docs/AMDGPU/gfx10_vdata1.rst
    R llvm/docs/AMDGPU/gfx10_vdata1_1.rst
    A llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst
    A llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst
    R llvm/docs/AMDGPU/gfx10_vdata_1.rst
    R llvm/docs/AMDGPU/gfx10_vdata_10.rst
    A llvm/docs/AMDGPU/gfx10_vdata_15d255.rst
    R llvm/docs/AMDGPU/gfx10_vdata_2.rst
    R llvm/docs/AMDGPU/gfx10_vdata_3.rst
    A llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
    R llvm/docs/AMDGPU/gfx10_vdata_4.rst
    A llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
    R llvm/docs/AMDGPU/gfx10_vdata_5.rst
    A llvm/docs/AMDGPU/gfx10_vdata_56f215.rst
    R llvm/docs/AMDGPU/gfx10_vdata_6.rst
    A llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst
    R llvm/docs/AMDGPU/gfx10_vdata_7.rst
    R llvm/docs/AMDGPU/gfx10_vdata_8.rst
    A llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
    R llvm/docs/AMDGPU/gfx10_vdata_9.rst
    A llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
    A llvm/docs/AMDGPU/gfx10_vdata_c08393.rst
    A llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
    A llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst
    A llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst
    R llvm/docs/AMDGPU/gfx10_vdst.rst
    R llvm/docs/AMDGPU/gfx10_vdst_1.rst
    R llvm/docs/AMDGPU/gfx10_vdst_10.rst
    R llvm/docs/AMDGPU/gfx10_vdst_11.rst
    R llvm/docs/AMDGPU/gfx10_vdst_12.rst
    R llvm/docs/AMDGPU/gfx10_vdst_13.rst
    R llvm/docs/AMDGPU/gfx10_vdst_2.rst
    R llvm/docs/AMDGPU/gfx10_vdst_3.rst
    A llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst
    R llvm/docs/AMDGPU/gfx10_vdst_4.rst
    A llvm/docs/AMDGPU/gfx10_vdst_463513.rst
    A llvm/docs/AMDGPU/gfx10_vdst_473a69.rst
    A llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
    A llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst
    R llvm/docs/AMDGPU/gfx10_vdst_5.rst
    A llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
    R llvm/docs/AMDGPU/gfx10_vdst_6.rst
    A llvm/docs/AMDGPU/gfx10_vdst_69a144.rst
    R llvm/docs/AMDGPU/gfx10_vdst_7.rst
    A llvm/docs/AMDGPU/gfx10_vdst_719833.rst
    R llvm/docs/AMDGPU/gfx10_vdst_8.rst
    A llvm/docs/AMDGPU/gfx10_vdst_89680f.rst
    R llvm/docs/AMDGPU/gfx10_vdst_9.rst
    A llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
    A llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst
    A llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst
    A llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
    A llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
    R llvm/docs/AMDGPU/gfx10_vsrc.rst
    R llvm/docs/AMDGPU/gfx10_vsrc_1.rst
    R llvm/docs/AMDGPU/gfx10_vsrc_2.rst
    R llvm/docs/AMDGPU/gfx10_vsrc_3.rst
    A llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst
    A llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst
    A llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst
    A llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst
    M llvm/docs/AMDGPU/gfx10_waitcnt.rst
    A llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst

  Log Message:
  -----------
  [AMDGPU][DOC][NFC] Updated GFX10 assembler syntax description

The description has been updated to reflect AMDGPU MC changes:
- enabled literals for src0 of v_fmaak_f*, v_fmamk_f*, v_madak_f32, v_madmk_f32;
- enabled global_atomic_fcmpswap and global_atomic_fcmpswap_x2;
- enabled dlc with flat_atomic* and global_atomic_*.

Bug fixing and improvements:
- enabled s_wait_idle;
- enabled s_waitcnt_depctr;
- added description of s_waitcnt_depctr syntactic sugar;
- disabled SYSMSG_OP_HOST_TRAP_ACK (it is not supported on GFX10);
- corrected description of lgkmcnt (accept values from 0 to 63).




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