[all-commits] [llvm/llvm-project] 7e8ff9: AArch64/GlobalISel: Regenerate mir test checks

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e8ff962b315a2462e6b9e2804a6bfade887b310
      https://github.com/llvm/llvm-project/commit/7e8ff962b315a2462e6b9e2804a6bfade887b310
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
    M llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir

  Log Message:
  -----------
  AArch64/GlobalISel: Regenerate mir test checks

Minimizes the test diffs in future changes from introduction of -NEXT.


  Commit: 5a5034d5081be4419ed464cc15d3af62426c0247
      https://github.com/llvm/llvm-project/commit/5a5034d5081be4419ed464cc15d3af62426c0247
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
    M llvm/test/MachineVerifier/test_g_load.mir
    M llvm/test/MachineVerifier/test_g_store.mir

  Log Message:
  -----------
  GlobalISel: Verify atomic load/store ordering restriction

Reject acquire stores and release loads. This matches the restriction
imposed by the LLParser and IR verifier.


Compare: https://github.com/llvm/llvm-project/compare/7ccd026cf281...5a5034d5081b