[all-commits] [llvm/llvm-project] 203a1e: Reapply "AMDGPU: Remove AMDGPUFixFunctionBitcasts ...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 203a1e36ed759e82c318c4066a8ad34c11b7d522
      https://github.com/llvm/llvm-project/commit/203a1e36ed759e82c318c4066a8ad34c11b7d522
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    R llvm/lib/Target/AMDGPU/AMDGPUFixFunctionBitcasts.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll

  Log Message:
  -----------
  Reapply "AMDGPU: Remove AMDGPUFixFunctionBitcasts pass"

This reverts commit 8a85be807bd453eb9c88d0126c75fd5ea393f60d.

The unrelated failure this exposed was fixed.


  Commit: 463bc93e5f57729d4bd7c5478f1e634987188514
      https://github.com/llvm/llvm-project/commit/463bc93e5f57729d4bd7c5478f1e634987188514
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h

  Log Message:
  -----------
  AMDGPU/GlobalISel: Remove unused parameter


  Commit: 492d0eab894f488b42d595d3bdc0c199fa624459
      https://github.com/llvm/llvm-project/commit/492d0eab894f488b42d595d3bdc0c199fa624459
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir

  Log Message:
  -----------
  AArch64/GlobalISel: Remove IR section from a test


  Commit: 3f3ff0e4309ac317ebea3e44188751451b88862f
      https://github.com/llvm/llvm-project/commit/3f3ff0e4309ac317ebea3e44188751451b88862f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir

  Log Message:
  -----------
  Mips/GlobalISel: Remove test IR sections and regenerate checks


  Commit: 4c037bdbab29e29ae371c6c9370b49b5b8d75ec9
      https://github.com/llvm/llvm-project/commit/4c037bdbab29e29ae371c6c9370b49b5b8d75ec9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Add more tests for inreg extend + load combine


  Commit: eee82dc66d61c842f9edff1ee80315b5a8d80870
      https://github.com/llvm/llvm-project/commit/eee82dc66d61c842f9edff1ee80315b5a8d80870
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Add some additional IR tests for zextload


  Commit: 1416744f8405db03096bc240a8ec9de176a71569
      https://github.com/llvm/llvm-project/commit/1416744f8405db03096bc240a8ec9de176a71569
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
    M llvm/test/CodeGen/AMDGPU/bfi_int.ll
    M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp

  Log Message:
  -----------
  GlobalISel: Implement computeKnownBits for overflow bool results


  Commit: d1f97a341958bb658e03bd8a01e9f19a9924d114
      https://github.com/llvm/llvm-project/commit/d1f97a341958bb658e03bd8a01e9f19a9924d114
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
    M llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir

  Log Message:
  -----------
  GlobalISel: Add memSizeNotByteSizePow2 legality helper

This is really a replacement for memSizeInBytesNotPow2 that actually
does what most every target wants. In particular, since s1 rounds to 1
byte, it wasn't lowered by this predicate. This results in targets
needing to think harder and add more matchers to catch all the
degenerate cases.

Also small bug fix that prevented the correct insertion of
G_ASSERT_ZEXT in the AArch64 use case.


Compare: https://github.com/llvm/llvm-project/compare/2291705d2b34...d1f97a341958