[all-commits] [llvm/llvm-project] 2ce256: [RISCV][SelectionDAG] Add a hook to sign extend i3...

Craig Topper via All-commits all-commits at lists.llvm.org
Mon Apr 11 14:40:27 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ce25628760ab2bbab764fc48c086704b4d6e279
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-11 (Mon, 11 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/aext-to-sext.ll

  Log Message:
  [RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64.

Materializing constants on RISCV is simpler if the constant is sign
extended from i32. By default i32 constant operands of phis are
zero extended.

This patch adds a hook to allow RISCV to override this for i32. We
have an existing isSExtCheaperThanZExt, but it operates on EVT which
we don't have at these places in the code.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D122951

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