[all-commits] [llvm/llvm-project] 700464: [RISCV] Only try LUI+SH*ADD+ADDI for int materiali...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 70046438d02ba1ec6bc2e2fc496b610cc1068b0f
      https://github.com/llvm/llvm-project/commit/70046438d02ba1ec6bc2e2fc496b610cc1068b0f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-09 (Sat, 09 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/test/CodeGen/RISCV/imm.ll

  Log Message:
  -----------
  [RISCV] Only try LUI+SH*ADD+ADDI for int materialization if LUI+ADDI+SH*ADD failed.

There's an assert in LUI+SH*ADD+ADDI materialization that makes sure the
lower 12 bits aren't zero since that case should have been handled as
LUI+ADDI+SH*ADD. But nothing prevented the LUI+SH*ADD+ADDI checks from
running after the earlier code handled it.

The sequence would be the same length or longer so it wouldn't replace
the earlier sequence, but the assert happened before that was checked.

The vector holding the sequence also wasn't reset before the second
check so that guaranteed the sequence would never be found to be
shorter.

This patch fixes this by only trying the second expansion when the
earlier fails.

Fixes PR54812.

Reviewed By: benshi001

Differential Revision: https://reviews.llvm.org/D123406