[all-commits] [llvm/llvm-project] 3d4bb7: [X86][SSE] combineSelect - more aggressively creat...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3d4bb78fbe620e5ec930fb7070e7e0d3daa47a2c
      https://github.com/llvm/llvm-project/commit/3d4bb78fbe620e5ec930fb7070e7e0d3daa47a2c
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-04-09 (Sat, 09 Apr 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll

  Log Message:
  -----------
  [X86][SSE] combineSelect - more aggressively create zero elements in the or(pshufb(x), pshufb(y)) fold

When we fold vselect(cond, pshufb(x), pshufb(y)) -> or(pshufb(x), pshufb(y)), ensure we convert all undef elements to zero elements - this should help us expose more known zero elements for deeper chains of these cases.

Noticed while triaging Issue #54819