[all-commits] [llvm/llvm-project] 1903b9: [RISCV] Always select (and (srl X, C), Mask) as (s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1903b9915456e06c46e3014f8cc41f4471de28a0
      https://github.com/llvm/llvm-project/commit/1903b9915456e06c46e3014f8cc41f4471de28a0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-08 (Fri, 08 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv32zbt.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3).

SLLI is always compressible to C.SLLI as long as the source and dest
register is the same.

ANDI and SRLI are only compressible if the register is x8-x15. By
using SLLI we have a better chance of generating shorter code.

I had to exclude one exclusion for the BEXTI case so that it's
pattern match could still fire.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D123336