[all-commits] [llvm/llvm-project] 3d4ca8: [CSKY] Correct the alignment of FPR register
Zi Xuan Wu (Zeson) via All-commits
all-commits at lists.llvm.org
Thu Apr 7 23:42:14 PDT 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 3d4ca8a8c39f772dd6c022220a6eef23238a77f6
https://github.com/llvm/llvm-project/commit/3d4ca8a8c39f772dd6c022220a6eef23238a77f6
Author: Zi Xuan Wu <zixuan.wu at linux.alibaba.com>
Date: 2022-04-08 (Fri, 08 Apr 2022)
Changed paths:
M llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
M llvm/lib/Target/CSKY/CSKYRegisterInfo.td
Log Message:
-----------
[CSKY] Correct the alignment of FPR register
The alignment of FPR64 and sFPR64 declared in RegisterClass should be 32 bit.
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