[all-commits] [llvm/llvm-project] 21949d: [mlir] Width parameterization of BitEnum attributes

[Jeremy Furtek via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 21949de62fa5ff71f24766f49ba09ddf9d65bd28
      https://github.com/llvm/llvm-project/commit/21949de62fa5ff71f24766f49ba09ddf9d65bd28
  Author: Jeremy Furtek <jfurtek at nvidia.com>
  Date:   2022-04-08 (Fri, 08 Apr 2022)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/include/mlir/IR/OpBase.td
    M mlir/tools/mlir-tblgen/EnumsGen.cpp
    M mlir/unittests/TableGen/EnumsGenTest.cpp
    M mlir/unittests/TableGen/enums.td

  Log Message:
  -----------
  [mlir] Width parameterization of BitEnum attributes

This diff contains:

- Parameterization of bit enum attributes in OpBase.td by bit width (e.g. 32
and 64). Previously, all enums were 32-bits. This brings enum functionality in
line with other integer attributes, and allows for bit enums greater than 32
bits.
- SPIRV and Vector dialects were updated to use bit enum attributes with an
  explicit bit width

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D123095