[all-commits] [llvm/llvm-project] 5e9022: [InstCombine] SimplifyDemandedUseBits - remove lsh...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5e90224839607b7a87f5d169e407dd5468d20265
      https://github.com/llvm/llvm-project/commit/5e90224839607b7a87f5d169e407dd5468d20265
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-04-07 (Thu, 07 Apr 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/modulo.ll

  Log Message:
  -----------
  [InstCombine] SimplifyDemandedUseBits - remove lshr node if we only demand known sign bit

This is a lshr equivalent to D122340 - if we don't demand any of the additional sign bits introduced by the ashr, the lshr can be treated as an ashr and we can remove the shift entirely if we only demand already known sign bits.

Another step towards PR21929

https://alive2.llvm.org/ce/z/6f3kjq

Differential Revision: https://reviews.llvm.org/D123118


  Commit: 5909c678831f3a5c1669f6906f777d4ec4532fa1
      https://github.com/llvm/llvm-project/commit/5909c678831f3a5c1669f6906f777d4ec4532fa1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-04-07 (Thu, 07 Apr 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

  Log Message:
  -----------
  [InstCombine] SimplifyDemandedUseBits - add TODO to remove shl node if we only demand known sign bits of the shift source

Similar to what we already perform for ashr/lshr


Compare: https://github.com/llvm/llvm-project/compare/1c1d477ce318...5909c678831f