[all-commits] [llvm/llvm-project] 7f14a1: AtomicExpand: Add NotAtomic lowering strategy

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f14a1d46b8e2233cbfb959e55ac9b7d33449c7e
      https://github.com/llvm/llvm-project/commit/7f14a1d46b8e2233cbfb959e55ac9b7d33449c7e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-06 (Wed, 06 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/AtomicExpandPass.cpp

  Log Message:
  -----------
  AtomicExpand: Add NotAtomic lowering strategy

Currently LowerAtomics exists as a separate pass which blindly
replaces all atomics. Add a new lowering strategy option to eliminate
the atomics which the target can control on a per-instruction level.


  Commit: e6012c8e0fbdf422325e66c96537de03d258deb7
      https://github.com/llvm/llvm-project/commit/e6012c8e0fbdf422325e66c96537de03d258deb7
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-06 (Wed, 06 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll

  Log Message:
  -----------
  AMDGPU: Handle private atomics

Use new NotAtomic expansion to turn these into the equivalent
non-atomic operations. Independent lanes cannot access the private
memory of other lanes, so there's no possibility for synchronization.

These don't really appear directly in user code, but
InferAddressSpaces can make these appear after optimizations.

Fixes issues 54693 and 54274.


Compare: https://github.com/llvm/llvm-project/compare/c4ea925f5048...e6012c8e0fbd