[all-commits] [llvm/llvm-project] 303c18: [MIPS] Initial support for MIPS-I load delay slots

[sdardis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 303c180199b73eb9c2840d05c92afeb9326e2e15
      https://github.com/llvm/llvm-project/commit/303c180199b73eb9c2840d05c92afeb9326e2e15
  Author: Simon Dardis <simon.dardis at gmail.com>
  Date:   2022-04-07 (Thu, 07 Apr 2022)

  Changed paths:
    M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.h
    M llvm/lib/Target/Mips/MipsSubtarget.cpp
    M llvm/lib/Target/Mips/MipsSubtarget.h
    M llvm/test/CodeGen/Mips/cpus.ll
    A llvm/test/CodeGen/Mips/mips1-load-delay.ll

  Log Message:
  -----------
  [MIPS] Initial support for MIPS-I load delay slots

LLVM so far has only supported the MIPS-II and above architectures. MIPS-II is pretty close to MIPS-I, the major difference
being that "load" instructions always take one extra instruction slot to propogate to registers. This patch adds support for
MIPS-I by adding hazard handling for load delay slots, alongside MIPSR6 forbidden slots and FPU slots, inserting a NOP
instruction between a load and any instruction immediately following that reads the load's destination register. I also
included a simple regression test. Since no existing tests target MIPS-I, those all still pass.

Issue ref: https://github.com/simias/psx-sdk-rs/issues/1

I also tested by building a simple demo app with Clang and running it in an emulator.

Patch by: @impiaaa

Differential Revision: https://reviews.llvm.org/D122427