[all-commits] [llvm/llvm-project] 34ce9f: [TLI] `TargetLowering::SimplifyDemandedVectorElts(...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34ce9fd864b58707d89c80361d42072442d47b55
      https://github.com/llvm/llvm-project/commit/34ce9fd864b58707d89c80361d42072442d47b55
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-04-06 (Wed, 06 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/madd.ll
    M llvm/test/CodeGen/X86/shrink_vmul.ll
    M llvm/test/CodeGen/X86/slow-pmulld.ll

  Log Message:
  -----------
  [TLI] `TargetLowering::SimplifyDemandedVectorElts()`: narrowing bitcast: fill known zero elts from known src bits

E.g. in
```
%i0 = zext <2 x i8> to <2 x i16>
%i1 = bitcast <2 x i16> to <4 x i8>
```
the `%i0`'s zero bits are known to be `0xFF00` (upper half of every element is known zero),
but no elements are known to be zero, and for `%i1`, we don't know anything about zero bits,
but the elements under `0b1010` mask are known to be zero (i.e. the odd elements).

But, we didn't perform such a propagation.

Noticed while investigating more aggressive `vpmaddwd` formation.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D123163