[all-commits] [llvm/llvm-project] 251637: [AArch64] Enhance last active true vector combine

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 251637690ab486bd13d8408453314aa933501dd0
      https://github.com/llvm/llvm-project/commit/251637690ab486bd13d8408453314aa933501dd0
  Author: zhongyunde <zhongyunde at huawei.com>
  Date:   2022-04-06 (Wed, 06 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-extract-element.ll

  Log Message:
  -----------
  [AArch64] Enhance last active true vector combine

Last active extracting will output LASTB + WHILELS, and the WHILELS itself
is a flag-setting operation, so perform it preferly.

Reviewed By: paulwalker-arm, sdesmalen

Differential Revision: https://reviews.llvm.org/D122551