[all-commits] [llvm/llvm-project] fa630e: [RISCV][AMDGPU][TargetLowering] Special case overf...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fa630e7594b6b6e771ffda4ddffec38cf3256e29
      https://github.com/llvm/llvm-project/commit/fa630e7594b6b6e771ffda4ddffec38cf3256e29
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-01 (Fri, 01 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV][AMDGPU][TargetLowering] Special case overflow expansion for (uaddo X, 1).

If we expand (uaddo X, 1) we previously expanded the overflow calculation
as (X + 1) <u X. This potentially increases the live range of X and
can prevent X+1 from reusing the register that previously held X.

Since we're adding 1, overflow only occurs if X was UINT_MAX in which
case (X+1) would be 0. So this patch adds a special case to expand
the overflow calculation to (X+1) == 0.

This seems to help with uaddo intrinsics that get introduced by
CodeGenPrepare after LSR. Alternatively, we could block the uaddo
transform in CodeGenPrepare for this case.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D122933