[all-commits] [llvm/llvm-project] 62dd36: [RISCV] Supplement SDNode patterns for vfwmul/vfwa...

[WangLian via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 62dd3674bcf88f60077460f80b6444fb7ac0adf4
      https://github.com/llvm/llvm-project/commit/62dd3674bcf88f60077460f80b6444fb7ac0adf4
  Author: Lian Wang <Lian.Wang at streamcomputing.com>
  Date:   2022-04-01 (Fri, 01 Apr 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll

  Log Message:
  -----------
  [RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D122720